Nicholas Fry, Ignacio Alzugaray, Mark Pupilli +2 more
This is the first 3D Gaussian renderer built for an Intelligence Processing Unit: 1,472 independent tiles, each with only on-chip SRAM and no shared memory pool to fall back on. The authors note those constraints approximate what efficient sensor-processor architectures look like, which is the real motivation.
The design follows from the hardware. Each tile owns a region of the framebuffer, and Gaussian primitives are routed to whichever tile needs them by hopping between neighbours in the four compass directions. Rendering becomes a communication problem as much as an arithmetic one, since a primitive's data has to physically travel to the tile that will draw it.
The interest is in what it demonstrates rather than in frames per second. If reconstruction can run on an architecture like this, the computation can move to where the sensor is instead of shipping imagery to a GPU somewhere else, which is a different shape of system entirely.
We present the first implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU), comprising 1,472 independent tiles with only on-chip SRAM; constraints that approximate properties of efficient sensor-processor architectures. Our input scenes are 3D Gaussian maps from real-world sequences. Each tile 'owns' a screen-space region of the framebuffer; Gaussian primitives are routed to destination tiles via Manhattan-distance hops on a north-east-west-south…
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