Neural recording chips spend a lot of their power just shipping data off the electrode. This work is a custom analog front-end chip that tries to spend less, by encoding signals as sparse events rather than a steady stream of samples, in the spirit of how neurons themselves communicate.

The ASIC carries 32 independently configurable channels, each able to output in one of two event-based schemes: pulse frequency modulation, or an adaptive delta modulator that auto-scales its data rate to the signal's envelope in real time. When the signal is quiet it emits little; when active, more. That adaptivity is where the compression, and the power savings, come from, which the authors aim at wireless neural interfaces. It's fabricated in a 180 nm CMOS process and meant to feed spiking neural network processors downstream.

This is a circuit-design paper, so the fabricated measurements and power figures in the full text are what matter.